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LeapEMU

LeapEMU

Product Description

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Target Applications

Terminal Devices

Applications

Documentation

Features

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Overview

LeapEMU is a high-performance, modular, and extensible RISC‑V emulator software suite that includes a hypervisor, a RISC‑V simulator, platform firmware, and a development toolchain. The hypervisor integrates the suite by configuring the platform firmware and system images (including the development toolchain) and invoking the RISC‑V simulator. LeapEMU is designed to accelerate the development, verification, and testing of RISC‑V RVA23 ecosystem software, enabling developers to build toolchains, benchmark applications, operating systems, and application software even before hardware is available, thereby significantly shortening development cycles and reducing costs. LeapEMU is offered in three editions: Community, Commercial, and Custom. The Community edition is freely available; the Commercial and Custom editions require a license—please contact Yueshang Technology.

Features

• Full instruction coverage of RVA23

• Ultra-high-performance simulation with over 128 cores

• Enterprise-grade reliability

• High-Speed Peripheral Virtualization

• Scene Optimization Acceleration

• Custom Instruction Set Sandbox

LeapEMU overall architecture

Features

Functions		Community Edition	Commercial Edition	Customized Edition
Hypervisor	Graphical Management	✓	✓	✓
	Virtual Machine Monitoring	✓	✓	✓
	Virtual Machine Device Management	✓	✓	✓
	Virtual Machine Network Management	✓	✓	✓
	Session Management	✓	✓	✓
	Invokes High-Performance RISC-V Emulator	✓	✓	✓
	Virtual Machine Creation Wizard	✓	✓	✓
	Virtual Machine Operations	✓	✓	✓
	Virtual Machine Configuration	✓	✓	✓
	Support Center Link	✓	✓	✓
	Online Community Link	✓	✓	✓
	Upgrade Link	✓	✓	✓
	Host Hardware and Virtual Machine Firmware Licensing	✕	✓	✓
	Custom Configuration	✕	✓	✓
	Snapshot Management	✕	✓	✓
	Debugging Log Management	✕	✕	✓
High-Performance RISC-V Emulator	RVA23	✓	✓	✓
	Emulated Hardware	✓	✓	✓
	Binary Dynamic Translation	✓	✓	✓
	APLIC Component	✓	✓	✓
	vI/O Thread Pool	✓	✓	✓
	IOMMU Component	✓	✓	✓
Platform Firmware	vCPU Boot	32 Cores	Over 128 Cores	Over 128 Cores
	Multi-Core Boot Optimization	✕	✓	✓
	Secure Boot	✕	✓	✓
	RAS Validation	✕	✕	Option
	RPMI Management	✕	✕	Option
Development Toolset	Compatible with Mainstream Linux Distributions	✓	✓	✓
	DevOps Toolset	✕	✕	✓
	Performance Testing Toolset	✕	✕	✓
	Binary Migration Toolset	✕	✕	✓
	Multi-Language Compilation Toolset	✕	✕	Option

Comprehensive support for experience optimization of the RISC-V software ecosystem

LeapEMU Application Scenarios

Chip Developers

LeapEMU provides chip design companies with a system-level verification environment prior to tape-out. Developers can run the full software stack in advance to validate the instruction set, multi-core scheduling, and peripheral interactions, significantly reducing the risk and cost of first-time tape-out failures.

Application Developers

Before RISC-V hardware compliant with the RVA23 standard becomes widely available, application developers can leverage LeapEMU’s standard environment to perform operating system porting, software development, and performance debugging ahead of time, ensuring that their software will seamlessly integrate with future hardware and greatly shortening the adaptation cycle.

Ecosystem Developers

For partners such as operating system distributors, LeapEMU offers an automated toolchain that supports batch compilation, testing, and validation of tens of thousands of software packages on the RISC-V architecture, helping to achieve synchronized releases across multiple architectures including x86 and ARM.

Education and Research

LeapEMU provides universities and research institutions with a low-cost, standardized RISC-V experimental platform. It removes the barrier of physical hardware requirements, making it easier to conduct teaching in courses such as operating systems and compiler design, as well as cutting-edge academic research.

End Users

End users can conveniently experience RISC-V ecosystem applications through LeapEMU, gain an intuitive understanding of their performance and compatibility, and provide real-world usage feedback for ecosystem optimization, thereby jointly promoting the maturation and improvement of RISC-V technology.